makefile - How to use pattern-dependent variables in dependencies in make pattern rules -

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I want to define GNU vs pattern rule with dependence in a pattern-dependent variable. What do I like: 

 % Exe: $ (% _ EXE_SOURCES) $ (% EXE_RESOURCES) $ (CSC_V) $ (CSC) $ (CSCFLAGS) $ ($ * $ * _EXE_CSCFLAGS) - Goal: exe \ -out: $ @ $ ($ * _ EXE_SOURCES) $ ($ * _ EXE_RESOURCES)

and later 

  FOO_EXE_SOURCES = src / Foo.cs all: Foo.exe

works to introduce the rule; In the body of the rule, the $ ($ * _ EXE_SOURCES) variable is expanded to $ (FOO_EXE_SOURCES) , which is src / Foo.cs . Dependence is not properly expanded, however; The changing source / FU COE does not give reason for rebuilding Foo.exe

I doubt that it can not really be made, but possibly someone has a job - make the piece evenly? You can use "secondary extension" to do something you are looking for:

/ P> 

  Foo_EXE_SOURCES: = foo.cs bar.cs baz.cs All: Foo.exe .SECONDEXPANSION:% .exe: $$ ($$ * _EXE_SOURCES) $ (CSC_V) $ (CSC) $ (CSCFLAGS) $ ($ * _ EXE_CSCFLAGS) - Targeted: exe \ -out: $ @ $ ($ * _ EXE_SOURCES) $ ($ * _ EXE_RESOURCES)

Enabling secondary extension In the prerequisites list, it is allowed to use automatic variables (i.e. $ * in this case), which is something that is otherwise not At will.


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